资源列表
2
- 详细功能、包含内容说明 :时钟2倍频vhdl描述,-It very important data
led8x8
- 8x8点阵滚动字幕显示驱动 verilog-8x8 dot matrix display driver verilog marquee
codeb_generator5.6
- B码校时（B码的产生）用来产生B码，实现B码校时 使设备进行同步。
xilinx_fpga
- 赛林思fpga开发实例包括verilog语言和vhdl语言-The Sailin Si fpga development Examples include the verilog language and vhdl language
lab1_VHDL
- VHDL数字系统设计工程实践，包含实验的原理，真值表和结构图描述，以及相关的VHDL代码。-VHDL digital system design engineering practice, including the principle of the experiment, truth table and chart descr iptions, and associated VHDL code.
kt3tuo
- 基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯-Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
alu_74181
- 4 bit alu to replace a 74LS181
p2s
- 并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
robertvision
- 基于FPGA的嵌入式机器人视觉识别系统模块源代码，也包括了所有硬件设计资料，是VERILOG格式-Embedded FPGA-based Robot Vision Recognition System module source code, including all hardware design information
xianshi
- spartan-3e lcd 字符滚动显示-spartan-3e lcd display characters rolling
FPGA_SDRAM_PCI
- 一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
nachosPipe
- nachos实验 操作系统实验 管程同步机制 消费者和生产者为例 改编原先版本中的一点小错误-nachos experimental test tube process operating system, consumers and producers as an example synchronization mechanism adapted the original version of a small error