资源列表
adc16bit
- ADC — 16bit-adc 16bit
Q24DTU-hardware-design
- Q24DTU硬件设计图，针对Q24完整硬件设计-Q24DTU hardware design, hardware design for the Q24 full
UCOS_II-transplant
- uCOS_II 在NiosII处理器上的移植过程以及全部源代码-uCOS_II NiosII processor in the transplant process and the full source code
UART
- 利用FPGA接受232芯片的串口数据，可以与PC进行串口通信-FPGA chip using the serial data received 232, serial communication with PC
verilogshuzishizhong
- 数字时钟的实验，让读者了解数字时钟的原理，用vhdl实现它的方法，并学习vhdl的使用技巧-Digital clock experiments, so that readers understand the principles of digital clock using vhdl way to achieve it, and learn skills to use vhdl
RF24L01yaokong
- MSP430F149—nRF24L01的全双工通信程序，发送端通过按键发送键值，接受端接受并用LCD显示。-MSP430F149-nRF24L01 full-duplex communication process, sender to send keys through the key, the receiving end to accept and use the LCD display.
PS2
- 此代码是PS2键盘的Verilog程序，键盘的字符可显示在LCD 1602上，经上板调试程序是可行的-This code is a PS2 keyboard Verilog program, keyboard characters can be displayed on the LCD 1602, after the board debug process is feasible
uart
- 状态机实现的可配置uart模块，经过fpga验证-State machine implementation can be configured to uart module, after verification fpga
keybord
- 用Verilog语言实现4*4键盘扫描程序-using Verilog keyboard4*4
fsmled
- verilog语言, 状态机实现数码管显示 -This uses verilog language to make state machine realization of digital control
SDRAM-control
- SDRAM控制器的Verilog源代码，主要用于SDR-SDRAM-SDRAM controller
gen_nx64k
- N×64K数控分频模块，可将2.048M时钟分频为一个NX64k的时钟，在E1复用设备上应用。 -N × 64K NC frequency module can be 2.048M NX64k clock frequency for a clock, the E1 multiplexing equipment apply.