资源列表
ALU1
- ALU 指令格式(16位） op DR SR fun 0--3 4—7 8--11 12--15 指令类 OP码 指令 FUN 功能描述 控制 0000 NOP 0000 空指令 HLT 0001 停机 有条件跳转 0010 JZ 0000 Z=1，跳转 JC 0001 C=1，跳转 JNC 0010 C=0，跳转 JNZ 0100 Z=0，跳转 Jump 0101 无条件跳转 LOAD 001
ADC_VHDL2
- analog to digital converson programmed in VHDL
fqdpsk
- provide an example for how to achieve fqdpsk
res
- verilog下fpga4路抢答器，有数码管显示和蜂鸣-verilog next fpga4 Road Responder, a digital display and buzzer
encode
- 8位优先编码器。 8位优先编码器。-8-bit priority encoder. 8-bit priority encoder. 8-bit priority encoder.
Crack_modelsim_6.1g-6.3d
- modelsim的学习和使用已经源代码，对读者很有帮助，如何使用modelsim builder-modelsim builder,very helpful
c_wp260
- 利用 Xilinx FPGA 和存储器接口 生成器简化存储器接口-Using Xilinx FPGA and the memory interface generator to simplify memory interface
uart
- 采用VHDL语言编写的串口驱动程序，已调试通过，能够实现同PC机的数据传输，可读性好，可移植性好-VHDL language using the serial driver has been debugged, to achieve the same PC, the data transmission, readable and portable
VHDL-radar
- 脉冲多普勒雷达回波信号相干积累的VHDL源程序-Coherent pulse Doppler radar echo signal accumulation VHDL source code ，it is easy to use
SRAM
- sram读写验证，用verilog写成，简单-sram module for test
liushuideng
- 本实验为LED流水灯实验. 本实验为LED流水灯实验.-In this study, experiments for the LED lights running water. This experiment LED water lamp experiment. This experiment LED water lamp experiment.
FPGA_traffic-lights
- 基于FPGA实现的交通灯verilog演示程序-FPGA-based implementation of the traffic lights verilog demo