资源列表
fir_16
- fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
FPGA_UART
- FPGA串口实现。 发送和接受数据功能代码-FPGA serial interface. Send and receive data function code
lowfrequencyphasemeasurement
- 原创代码--绝对值得下载 低频相位测量原代码， 测量精度可到10^-6次方，测量范围1hZ-30M -Original code- definitely worth downloading the original source of low-frequency phase measurement, the measurement accuracy can be 10 ^-6 power, range 1hZ-30M
8.4ADC0809
- FPGA中用VHDL编写的AD0809的转换接口电路及程序源码-FPGA using VHDL prepared AD0809 conversion interface circuit and program source code
nios-II
- 很好地描述了NOISII的串口、定时中断等各种实例-A good descr iption of the NOISII the serial port, timer interrupt, and other examples of
sdram-source
- SDR SDRAM 控制器的源代码 altera公司的-source code from altera
vga_gen
- VGA Control with VHDL in Altera DE0 Board
ncvlog
- Cadence NC-verilog user guide C adence NC-verilog user guide C adence NC-verilog user guide Cadence NC-verilog user guide-Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user gu
vhdlclock
- EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
fifolifo
- fifo filo verilog 程序！先入先出数据存储器的程序和先入后出程序！-fifo filo verilog program! First in first out data memory of the program!
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
key
- verilog键盘防抖程序，很有实用性 verilog键盘防抖程序，很有实用性-Reduction procedures verilog keyboard is very practicalReduction procedures verilog keyboard is very practicalReduction procedures verilog keyboard is very practical