资源列表
RR_SCH(Executable)
- FPGA VERILOG调度器一般包括SP、RR、WRR、WFQ等，RR调度指的是轮询调度，此种调度不带权重概念，均匀轮询进行调度。-FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
ao486-master
- 这是一个开源的486SX IP CORE对X86硬件感兴趣的可以参考一下，已经仿真通过了-is a op source 486 processor ip core ,study x86 cpu be refence is
KCPSM6_Release5_30Sept12(Virtex6)
- XIlinx Virtex-6 （Spartan6及7系列）的PicoBlaze的源代码（官网转载），与用于Virtex2、Spartan3的不一样！-Xilinx Virtex-6 (Spartan6-and 7 series), the PicoBlaze the source code (the official website reproduced) with for Virtex2, the Spartan3' s not!
am
- 利用altera的cyclone FPGA芯片，实现AM调制，并使用自带的逻辑分析仪仿真成功。-The use altera cyclone FPGA chip, AM modulation, and use its own logic analyzer successful simulation
Altium_Designer_FPGA
- 基于Altium Designer 6.0的FPGA开发-Altium Designer 6.0 Based on the FPGA development
VHDL-XILINX-EXAMPLE26
- [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现AD
CD1_MT9V032C_RAW_DISPALY_TRANS
- MT9V032C_的FPGAnios程序，亲测能用-dfgdfg dfgdfg0.
ds1302
- 使用verliog设计实现驱动DS1302，利用altera的cyclone第四代验证通过-Design and implementation using verliog drive DS1302, use altera' s fourth-generation verified by cyclone
vga_3
- VGA关于FPGA的图层概念，能很好理解VGA的工作原理-VGA layer concept of the FPGA can well understand VGA works
PS2-keyboard
- DE2-115实现键盘输入显示在lcd显示屏-DE2-115 keyboard input and show in the lcd
Of-EDA-technologies-with-Verilog_HDL
- EDA技术与Verilog_HDL的红模块和IP应用的理论知识和实例分析-Of EDA technologies with Verilog_HDL
LCD_test
- 用Verilog描述的，基于FPGA的直接LCD显示程序代码-Described using Verilog, FPGA-based LCD display program code directly