资源列表
VmodTFT-Simple-Paint-DEMO
- VmodTFT Simple Paint DEMO VHDL tftlcd driver
FPGA_Vision
- 该源码为基于FPGA的工业现场实时监控界面的设计，本模块可实际运用于FPGA工业应用场合，也可以作为FPGA设计的参考-The source code for the FPGA-based industrial real-time monitoring interface design, the module can be used in the actual application of FPGA industry applications, can also be used as a ref
AM
- Quarus环境下用VHDL语言和IP核实现AM调制-Realization of AM with VHDL and IP core under Quartus environment
HDLC_FPGA
- HDLC接口协议的FPGA实现,使用Verilog hdl-FPGA HDLC interface protocol implementation using Verilog hdl
hdlc
- HDLC接口协议的FPGA实现使用verilog-design of HDLC
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
norflash
- 程序和数据可存放在同一芯片上，拥有独立的数据总线和地址总线，能快速随机读取-Programs and data can be stored on the same chip, an independent data bus and address bus, fast random read
lab1
- Xilinx官方提供的六个 EDk实验中实验一的工程文件。-The official Xilinx provides six EDk experimental a project file.
sdram_control.RAR
- 基于XILINX FPGA的SDRAM 控制器代码。VERILOG HDL代码编写-SDRAM CONTROLER
class11_uart_tx
- 主要是使用Verilog代码编程的串口发送程序-Mainly use Verilog code programming serial port to send the program
or1200.tar
- OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
1
- 基于FPGA实现FIR数字滤波器的研究 -FPGA-based realization of FIR digital filter FPGA-based realization of FIR digital filter