资源列表
FIFO
- 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
T_uart
- CPLD发送模块的实现代码,设计按键检测模块，并将键值通过构造的UART发送模块发送到串口调试工具中查看。--发送格式：1位起始位+8位数据位+1位停止位=10位-CPLD implementation of the code to send the module to design key detection module, and key by constructing the UART to send the module to send to the serial port debugg
GPIO1
- gpio controller source code verilog
fft
- 基于NIOS II的fft程序，使用C语言编写实现快速傅里叶变换-FFT based on NIOS II, using C language to realize the fast Fourier transform
trafficcontrol
- 十字路*通控制器,主,支路的交通灯控制,带左拐的信号灯.
stack_16x8
- VHDL语言写的16x8堆栈模块设计，存储器全满时给出信号并拒绝继续存入；读出时按后进先出原则；存储数据一旦读出就从存储器中消失；有相应的testbech文件，经测试可用。对小型设计很有用！欢迎下载交流学习。-Write VHDL 16x8 stack module design, memory signal is given full and refused to continue the deposit readout LIFO principle store data read out
verilog
- 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
pci1
- 如果想为了以后的2k平台兼容就最好编wdm，因为windows2k不支持vxd，而且以后的发展wdm肯定要代替vxd了。不过由于我找到的资料基本上都是介绍vxd的，感觉vxd的技术好像更成熟一点，编的人更多一点，所以偷了一下懒（惭愧），就没有去研究wdm，就选择了vxd。-If you want to later edit 2k on the best platform compatible wdm, because windows2k not support vxd, wdm and futu
qvgatiming
- QVGA的Timing verilog 描述
usart.rar
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order. ,USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
cc_encode
- 卷积码，并行编码，FPGA，通过了测试验证-CC Code， Parallel Coding， FPGA
ADset
- AD9222接收指令逻辑。（Verilog语言）-AD9222 to receive instruction logic. (Verilog language)