资源列表
msk_modulation
- 用verilog硬件描述语言写的msk调制程序,可以拿来参考一下-With verilog hardware descr iption language to write msk modulation process, you can refer
ahb_system_generator_latest.tar
- AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.
uart_fifo
- 一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。-This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.
traffic_controller
- 一款交通灯控制芯片的verilog源码，该源码通过仿真并在FPGA上运行成功，可以实现上位机操作控制交通灯的工作模式：两相模式和四相模式。上位机操作通过串口调试助手来完成。源码中与上位机的接口采用的是UART接口。-This is a verilog code for a kind of traffic light controller. The code was simulated and verificated on FPGA. When the code works on FPGA, it
cpu
- 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
rx_decode
- 对串行接收数据进行解码的功能，通过状态机实现，属于链路层协议的实现。-Serial reception data decoding function, by state machine, belonging to implement link layer protocol.
rs422_t
- 此功能模块实现了422标准协议的单字节发送功能，采用了起始位＋8位数据位+奇校验+1停止位的方式，实现了并行输入串行输出的功能。-This function module implements the standard protocols 422 single-byte transmit function, the start bit+ 8 data bits odd parity+1+ stop bits, enabling a parallel input serial output.
rs422_r
- 此功能模块实现了422标准协议的单字节接收功能，采用了起始位＋8位数据位+奇校验+1停止位的方式，实现了串行输入并行输出的功能。-This function module implements the standard protocols 422 single-byte receive function, using the start bit+ 8 data bits odd parity+1+ stop bits, enabling a serial input parallel outpu
clk_div
- 时钟分频功能模块，采用计数器后两位异或再移位的方式实现，节约资源。-Clock divider function module, after using two different counter or re-shift ways to save resources.
reset_syn
- 复位信号的处理，实现“异步清零，同步释放”的功能。-Reset signal processing, " asynchronous clear, synchronous release" function.
polyphaseFIR_1v0
- polyphase fir dilter
khanom-heydari
- Floaaattiing poiiint for vhd-Floaaattiing poiiint for vhdlll