资源列表
uart_fifo_transceiver_verilog
- verilog UART FIFO 自发自收 自己验证过 基于EP1C3T开发板的-Verilog UART FIFO internal loopback； tested； based on EP1C3T
OOO
- AES 低资源利用率的加密解密，状态机的使用，128位的-Encryption and decryption, the state machine of low resource utilization using AES 128-bit
SIV_ALTMEMPHY_DDR3
- ddr3 interface demo,
m-sequence_gen
- m序列生成verilog代码，经过仿真测试，绝对可用，带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
2^n-divor
- 2的n次方分频设计，可以实现任意分频。使用verilog编写-n th power of 2 crossover design, you can achieve any frequency. Use verilog to write
fir10order-verilog
- 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
3-ddc-cic_5hb_firmatlab-testbench)
- 三通道上下变频cic_5hb_firmatlab仿真程序-Three-channel down conversion cic hb fir matlab simulation program
1M_200k_-firstandard
- 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
tp
- It is a Verilog code for Morse code decoder.
scc
- It is a scanner Verilog code for 4*4 matrix keypad system. It reads the key which is pressed.
kbb
- It is a Verilog code for PS2 keyboard/mouse receiver interface. It is very easy to use.