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资源列表
AX301_jtag_uart_test
- 黑金AX301开发板，jtag口驱动及调试实验代码-AX301 development board,JTAG port driver and debug experiment code
AX301_led_test_code
- 黑金AX301开发板led相关实验程序代码-AX301 development board LED test code
pll_prj
- PLL配置仿真实验 PLL，即锁相环。简单的理解，给PLL 一个时钟输入（一般是外部晶振时钟）， 然后经过PLL 内部的处理以后，在PLL 的输出端口就可以得到一定范围的时钟频 率。其之所以应用广泛，因为从PLL 输出得到的时钟不仅仅从频率和相位上比较 稳定，而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
05413cordic
- VHDL CODE FOR CORDIC ALGORITHM
anish-bit-masking
- vhdl code for bit masking algorithm
AD9854(Altera)
- 这是个用FPGA编写的AD9854的驱动程序，它包含了FSK,PSK,ASK。-This is a written in FPGA driver of AD9854, it contains the FSK and PSK, ASK.
conv_encoder(rate=1_2)
- 这是用ISE编写的verilog语言1/2码率的卷积编码的代码-It is written in verilog language ISE convolution coding rate 1/2 code
QPSK
- 这是用ISE编写的verilog语言的QPSK调制的代码-This is the QPSK modulation verilog language written with ISE code
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
Interleaver_Deinterleaver
- 通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。-Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.
Random_Derandom
- 通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。-Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.
RS_Encode_Decode
- RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。-RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.