资源列表
cordic
- This attachment consists of the coordinate rotation digital computer algorithm code which is most use algorithm in signal processing
2-fsk
- 2-fsk调制解调的fpga实现。two-fsk为调制程序，fsk-two为解调程序。-2-fsk modulation and demodulation of fpga implementation. two-fsk for the modulation process, fsk-two for the demodulation process.
ALU
- ALU logic using Verilog
ADD
- ADD instruction for the HC08 Target
code_lock
- 密码锁,内部有密码的初始输入与设置密码,还有密码的鉴定.-Lock, internal code of the initial input and set the password, as well as the identification code.
uart
- 用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。-a veriog program completed on FPGA to contrlo a uart to communicaton with a computer
dac
- Delta sigma DAC for use in FPGA includes Testbench
clock
- 采用FPGA实现数字钟功能，包括调时调分整点报时等功能。-FPGA Implementation of a digital clock function, including the tune when the tune points the whole point timekeeping functions.
dac_test
- DAC_TLC5620测试模块，verilog语言-module of texting DAC_TLC5620
vga
- FPGA board universal VGA block
equalizer
- This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
cpu-kongzhi
- 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-