资源列表
we
- 用VHDL写的5级流水线的回写阶段，绝对好用-Using VHDL written five stage pipeline write-back, absolutely easy to use
spwm
- 关于SPWM调制设计VHDL代码 关于SPWM调制设计VHDL代码-SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM
clock
- 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
8b10btest
- lattice fpga serdes接口程序-lattice fpga serdes interface program
COUNT100
- 一个数字计数器，每100秒即输出一个脉冲信号，可用于定时控制-a digital counter, every 100 seconds is a pulse output signal can be used for timing control
crc_outlogic
- Cyclic Rdundancy Check.
uart1
- 使用VerilogHDL实现的一个串口，自己调试通过并实用-A usart program scr ipt with VerilogHDL program langrage, have used in applications!
clock18div
- Clock Divider, divfactor of 18
vhdl
- 基于FPGA的FSK 的实现！fsk的调制解调，相干与非相干解调！-Implementation of FPGA-based FSK! fsk modulation and demodulation, coherent and non-coherent demodulation!
ep2c5lcd1602
- LCD1602 interfacing routines for FPGA (EP2C5-EP2C8)
ntt
- NNT algorithm VHDL FPGA