资源列表
Freq_kx11
- 用51单片机的定时计数器0脉冲进行计数，并用LCD1602显示，如果脉冲特性好，精度可以达到1Hz，带宽1Hz-50KHz（系统时钟12M）-With 51 SCM timing counter pulse count, and 0 LCD1602 shows that if the pulse, precision can reach 1Hz, 1Hz bandwidth 50KHz- 12M clock (system).
1602A-VHDL
- --利用FPGA驱动LCD显示中文字符"年"的VHDL程序。 --文件名 ：lcd1602.vhd。 --功能 ： FGAD驱动LCD显示中文字符"年"。-- Using FPGA-driven LCD display Chinese characters " year" VHDL program.- File Name: lcd1602.vhd.- Function: FGAD drive LCD display Chinese characters " ye
i2cSlave_1
- This the first file that describes an i2CSlave interface.-This is the first file that describes an i2CSlave interface.
FJ8030_fpga.out
- 一种关于FPGA系统设计的时钟约束文件，可以直接添加到主模块以减少Unconstraint path-A timing constraints on FPGA system design documents
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
ram_dp_sr_sw
- VHDL源代码,资源多多共享,不懂的地方多多指教
frequency
- 一种等精度的频率计，同时适合高频和低频，误差小。-A precision frequency meter, etc. At the same time, suitable high-frequency and low frequency, the error small.
FSM_test
- FSM_test for textbanch in vhdl-FSM_test
synplify_makefile
- synplify、ise和verdi在linux上的makefile；多个工具集成在一个文件管理，方便快捷，值得参考-the makefile for synplify, ise and verdi on Linux multiple tools integrated into a document management, convenient and valuable reference! ! !
gf
- DDS use AD9852 with vhdl for director
STATE_9852
- FPGA控制DDS芯片AD9852，产生幅值和频率可调的正弦信号-FPGA control AD9852 state
ad5764
- 数模转换器AD5764的Verilog HDL源程序，已在项目中验证了其可行。-DAC AD5764 Verilog HDL source code, and have verified its feasibility in the project.