资源列表
PCK_CRC32_D8
- VHDL实现的8位数据，CRC32的实现代码，简单实用-VHDL achieve 8-bit data, CRC32 implementation of the code, simple and practical
stopwatch
- 在fpga上实现秒表计数器的设计，主要目的是实现对fpga基本的认识-Stopwatch counter on the fpga design, the main aim is to achieve understanding of the basic fpga
async-fifo
- Verilog codes for asynchrounous fifo design
SR_SerIn
- Shift Register, Serial In Parallel Out VHDL
spi_slave
- SPI功能模型，可以用于SPI的仿真验证工作，对其进行测试-Now for the SPI slave in the FPGA. Since the SPI bus is typically much slower than the FPGA operating clock speed, we choose to over-sample the SPI bus using the FPGA clock. That makes the slave code slightly more compli
ofdm_modu
- ofdm的verilog程序 利用ＦＰＧＡ实现
dco_12
- 是一个DCO的VHDL代码，源自Willey的博士论文，很好的一个源码，希望对各位有用。-The VHDL code is a DCO, from Willey' s doctoral thesis, a good source, and I hope you useful.
Temperature-Meter
- Temperature Meter in VHDL code.
test8
- 设计一个8路数据选择器，每路输入数据与输出数据位四位二进制的-Design of an 8-channel data selectors, each data bit input data and output four binary
AD9850-dds
- AD9850 DDS 驱动程序 下载值单片机即可使用-AD9850 DDS chip driver download value can be used
FIFO
- FIFO的功能众所周知，非常好的处理时序问题。(The functions of FIFO are known to be very good at dealing with timing problems.)
7segInitial
- 基于spartan3火龙刀系列FPGA开发板制作的7段数码管设计实验例程