资源列表
traffic_light
- 实现十字路口简单交通灯的verilog hdl源代码,可以实现
New-folder-(2)
- this is avhdl code for fir filter design
div50m
- 用VHDL代码编写的50分频器,已经经过Quarter仿真，证明正确，可用于计时器中-50 divider using VHDL code has After Quarter simulation, proved correct, can be used in the timer
ad7266
- 实现FPGA对AD7266的控制，采用Verilog语言编写-FPGA to achieve AD7266 control, using Verilog language
ITU_656_Encoder
- ITU_656协议下的图像编程代码，适用于此协议下传输图像的开发者-The image programming code under the ITU_656 protocol, suitable for transmission of images to developers under this Agreement
Versuch1.vhd
- Simply Hello World alias Hola with seven Segment unit
ApbGPIO
- PowerFull Apb GPIO Controller
uart
- Uart lite vhdl descr iption with properties to evaluate performances in data transmission and reception.
ir_module
- ir_module with verilog code for controller remote
sw_debounce
- 当三个独立按键的某一个被按下后，相应的LED被点亮；再次按下后，LED熄灭，按键控制LED亮灭 -When one of the three independent keys is pressed, the corresponding LED is lit once again, after the LED is out, the button control LED light off
FLASH_WR
- 本文件为用Verilog写的FLASH S29AL032D读和擦除的驱动时序，对刚学习Verilog的同学有一定帮助，已在DE2开发板上验证。-This document is written in Verilog FLASH S29AL032D read and erase the drive timing of the students just learning Verilog will definitely help, has verified the DE2 board.
UARTReceiver
- serial communication using uart FPGA-based embedded system