资源列表
baseband_code
- 利用VHDL硬件语言编写了常用的基带码的产生，Quartus ii 仿真通过。-Written by VHDL hardware language code commonly used in the generation of baseband, Quartus ii simulation pass.
F161xb8
- 模块名称：4位同步计数器模块 功能描述：完成4位同步计数器的功能-Module Name: 4 Synchronous Counter Module Descr iption: Complete four synchronous counter function
water_lamp
- 一个基于verilog的流水灯程序，一共有8个灯，到达边沿后自动返回，约束文件对应的是BASYS2的看法版-A water lamp procedures, based on verilog,
clk_div
- 时钟分频功能模块，采用计数器后两位异或再移位的方式实现，节约资源。-Clock divider function module, after using two different counter or re-shift ways to save resources.
sinwave
- 用verilog HDL产生正弦阶梯波。加da即可输出正弦波
corna
- 用vhdl语言实现在单片机上的加法操作，时序排列以及自动跑马功能-Using vhdl language implementation in the SCM on the addition operation, timing, and automatic Happy function arranged
DCDC
- 彩色灯控制小程序，控制RGB三中灯不花出不同的颜色。-Color light control applet in the control RGB light does not take three different colors.
sram_test
- is61lv25616简单的verilog程序，完成sram读写-is61lv25616 simple verilog program, complete sram read and write
counterdiv
- 用D触发器组成2分频电路，并对时钟进行计数-2-div frequency using D flip-flop circuit.
alu_struct
- ALU written in VHDL, tested in FPGA advantage, there will be no support on this code. All right reserved by developer.
floatingpointaddition
- floating point program for addition