资源列表
AdderE
- synplify中tcl语言应用，使用AdderE八位全加器为例，介绍一个设计针对不同器件综合-synplify in the tcl language application, use AdderE eight full-adder as an example, an integrated design for different devices
lcd.vhd
- 能够实现控制LCD显示的VHDL程序代码。-To achieve control of LCD display VHDL code.
modifiedVCO_WITH_PLL
- voltage controlled oscillator using VHDL
flow
- QuartusII 应用VHDL语言编写，实现数码管的扫描。-QuartusII using VHDL language, scanning the digital tube.
myAdc9248
- CycloneIV控制采样芯片AD9248-20MHz，VHDL语言-CycloneIV control sampling chip AD9248-20MHz, VHDL language
ADV7180
- this files describe how to configure an ADV7180a
main
- 基于FPGA的驱动诺基亚3310显示器驱动程序，模拟SPI传输模式-FPGA-based Nokia 3310 display driver drivers to simulate SPI Transfer Mode
AM_Modulation
- Am modulation implement fpga
S2P_TOP
- This file contains the top module which uses the S2P_SM module which is actually a controller. SO by changing in the top module we can use the S2P module completely-This file contains the top module which uses the S2P_SM module which is actually
lcd1602
- lcd1602的现实程序，可以在屏幕上逐行扫描-lcd1602 the reality of the procedure, you can scan the screen line by line
LCD-hello
- VHDL syntax hello world for LCD written in VHDL MAXII evaluation board EPM1270F256C5
sdfsdFifo
- 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out