资源列表
fixed-div
- 定点的除法运算代码，写的挺好的，一起分享一下。-Fixed-point division operation code, written in good, share it.
ps2scan
- ps2口的数据采集verilog源码，带测试程序-ps2 port data acquisition
8multipler
- 用VHDL实现8位移位相加乘法器，从被乘数的最低位开始，若为1，则乘数左移后与上次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。-VHDL 8-bit shift by adding the multiplier to achieve, starting from the lowest multiplicand, if 1, then left after the multiplier and add the last if 0, left after adding all 0, u
Rxing
- 1. 掌握将组件按需要组合起来，以R型指令为例，实现指令处理器功能。 2. 掌握寄存器组、ALU单元的工作原理和作用，以及组件的组合方法。-1 to master the necessary components together, the R-type instruction, for example, to achieve command processor function. 2 control registers, ALU unit works and the role and co
vgacolor
- vga编程。实现3种模式的vga控制，分别产生横彩条，竖彩条，棋格彩条的显示-vga programming. Realization of the three-mode vga control, generate horizontal color of the color of the shaft, and the chess grid color of the show
dianji
- QuartusII环境下，用于upds实验板的三相六拍电机-QuartusII environment, for the three-phase experimental board upds shot six motor
51LCD-adjustable-clock
- 51单片机液晶显示可调时钟，用于AT89S51液晶显示，可供参考-51 single-chip LCD adjustable clock
ClkDivide
- This my version of the unit which carries out the division of the input signal-This is my version of the unit which carries out the division of the input signal
CLK_Detector-
- 时钟（2m、34m、45m、58m、77m、155m)检测-CLOCK INCLUDING(2m、34m、45m、58m、77m、155m)DETECT
ds18b20vddl
- 传感器ds18b20 与 FPGA 通信 实现方式
FPGACOM.rar
- FPGA编程实现串口通信，源代码全。包括仿真程序。,FPGA programming serial communications, the entire source code. Including the simulation program.
fifo_csm
- 一个先进先出的描述代码，用于实现先入先出的操作-first in first out