资源列表
async_receiver
- Asynchronous receiver
linear_interpolation
- it use interpolate any thing
cpld-0809
- 这是利用VHDL语言编写的关于ADC0809的程序，编的很不错
spreadspectrum2
- these files are written in verilog but i am uploading in text format
LCD_Control
- 液晶1602的显示程序，固定显示几个汉字，修改汉字内容就可以用了-1602 LCD display program, fixed displays several characters, can be used to modify the content of a character
mon
- vhdl code for memory core
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
verilogdepwm
- 用verilog写的一个用FPGA产生PWM波的源码-Verilog
adc_tlc3548
- 用于FPGA连接的A/D转换芯片TLC3548-FPGA connections for A/D converter chip TLC3548
design-1-serially-transmit-name
- 8051 code to transmit name serially
rav2011
- 双向视频通讯，用于对讲系统，可以轻松用于其他应用-double video
morsecode
- 用DE2板，用SW0 到1表示想要的字母，KEY1运行，红灯显示对应的摩斯码，KEY0重置-With DE2 board with SW0 to 1 indicates the desired letter, KEY1 running red lights display the corresponding Morse code, KEY0 reset