资源列表
phase_measure
- 这是一个计算两个同种类型的信号的相位差的Verilog实现的代码-This is a calculation of two signals of the same type of implementation of the code phase of the Verilog
uart_tx
- 这是个UART发送的VHDL程序，调试过，还可以
Verilogobouttelephone
- verilog的一个电话设计的源代码，初学者和设计着可以参考-a phone designed for verilog source code, can refer to the beginners and design
dac7811_1
- DAC7811的驱动,VERILOG编写-The DAC7811 drive, VERILOG prepared
example5
- 此代码硬件开源代码,代码实现按键的功能,值得参考-This code is open source hardware, code key functions, it is also useful
Booth2_16
- 这是16位booth阶2的有符号乘法器及其相关测试程序-16 bit booth order 2 with symbolic multipliers and related test procedures
fdmk
- 键盘防抖模块Verilog硬件描述语言代码-Anti-Shake module keyboard Verilog hardware descr iption language code
Trafficlight
- 数字电路设计试验中用Verilog语言实现的 交通灯源码-Digital circuit design using Verilog language test traffic light source
tan
- LCD液晶屏驱动控制，基于51单片机，可以测试。调试成功-LCD panel drive control
SRAM
- 有关sram的控制器源代码 有需要的可以免费下载-Sram controller about the source code need free download
divider_32bitdivby16bit
- verilog代码实现的32位除以16位无符号整数除法器，在别人8位除法器的基础上改进完成，32个时钟周期完成一次运算。-verilog code for 32-bit divided by 16-bit unsigned integer divider it s based on other guy s 8 bit divider verilog code. it need 32 clock cycles to complete an operation.
mdio_mdc
- mdio verilog 实现-mdio verilog coding