资源列表
Verfication_Methodology
- SOC Verfication Methodology and Techniques
nios_uart.rar
- nios uart 在开发板上试过的，修改了，希望能有用,nios uart board tried in the development of
SYSTEM-ON-A-CHIP-Verification
- 芯片设计SoC验证书籍 SYSTEM-ON-A-CHIP-Verification-SYSTEM-ON-A-CHIP-Verification
State-Machine
- 这是个人整理的11篇有关状态机的资料，很有用。-This is a personal order of 11 information on the state machine, very useful.
calculator_vhdl
- Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB. -Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB.
uart-jiazhen
- 用 verilog 编写的串口通信程序，编译通过，代码完整，非常好用下载就可用，全力推荐新手使用-Using verilog prepared by the serial communication program, compile, code integrity, very easy to use you can download to use, fully recommended for newbies
sdramtEST
- sdram动态存储器测试的源文件工程，Quartus II 9.0 (32-Bit)版本。-sdram TEST
VGA_NEW
- VGA显示，黑金动力社区的例子，有很好的学习意义-VGA display, an example of the power of black gold community, have a good sense of learning
Racinggame
- 赛车游戏，VHDL数字系统设计，经过QUARTUS的验证，非常好用，有非常丰富的解释，游戏有赛道，碰赛道者挂，GAME OVER-Racing game, VHDL digital system design, through verification QUARTUS, very easy to use, has a very rich interpretation, games have the track circuit are linked to touch, GAME OVER
wola
- WOLA polyphase filter加权跌接累加FFT信道化技术-WOLA polyphase filter bank
IRDA
- 该代码利用veilong语言，能实现通过红外遥控让数码管显示相关数据-The code using veilong language, can be achieved through infrared remote control to allow the digital display of the relevant data
2-25
- 这个是有关抢答器的代码，主要是针对Verilog语言的，包含详细的模块设计图，设计文档以及整个模块设计的代码和架构图。-This is the code Responder Verilog language, contains a detailed module design, design documentation, as well as the entire module design code and architecture diagram.