资源列表
Div20PLL
- 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
phase
- 实现两路数字信号的鉴相功能，最后通过静态LED显示出来，该程序通过硬件的测试
WatchDog
- 对与单片机常用的功能看门狗，本程序用vhdl硬件语言实现次功能。
FPGA读写控制sram
- 拨码开关控制读写，按键控制地址加，读出数据由数码管显示，直观展现了程序是否正确。
fifo
- 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
2
- 图像分割，将运动图像从背景图像中提取出来。-Image segmentation, the moving image extracted from the background image.
adder4
- This example illustrates the use of the For Generate statement to construct a ripple-carry adder a full adder function. It also shows how to use a package -This example illustrates the use of the For Generate statement to construct a ripple-carry add
mcuconnect
- 基于VHDL语言开发的mcu与外部器件的接口程序，解决了高速mcu与低速外部器件的接口问题。-based on VHDL development mcu with external device interface, mcu solve the high-speed and low-speed external device interface.
mcuconnect
- 用VHDL来提高MCU的连接速度。对MCU有兴趣的朋友，值得下载一看。
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
lcd1602_vhdl_code
- 液晶lcd1602的vhdl源代码,测试FPGA上的LCD1602程序,下载到开发板就可使用-LCD lcd1602 the vhdl source code, test FPGA on the LCD1602 program downloaded to the development board can be used
paobiao
- 这主要是一个简单的实现的数字跑表，是我刚开始学FPGA时做的一个小实验-This is mainly a simple digital stopwatch, I just started to learn FPGA to do a little experiment