资源列表
key_expander
- This module is the package deceleration for Key Expander Hardware for each round
frequency-counter
- 这是使用VHDL语言编写的频率计数器源码。包含了各个模块以及主函数。-This is the source of the frequency counter using VHDL language. Contains various modules and the main function.
aFifo
- 异步fifo用verilog语言实现的完整代码，适用于数字前端的设计-This implementation is based on the article Asynchronous FIFO
vhdl_nik.tar
- these are simple vhdl test codes
freq
- 数字频率计：由一个测频控制信号发生器，八个有使能十进制计数器及一个32为寄存器组成-Digital frequency meter, eight energy decimal counter and a 32 for the registers: a frequency measurement control signal generator
TEST5
- 这个是秒表的程序,很简单,不要取笑,多多交流了-This is a stopwatch procedures, is very simple, do not make fun of, a lot of exchange of
ds18b20-vhdl
- vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange
awgn
- 高斯白噪声的VHDL实现。伪随机序列只能输出均匀噪声，需要打乱相关性。-awgn in vhdl
vga
- SPARTAN3AN VGA test it s for starters to get the idea about how to use vga port on spartan3an kit. in this code , first 50mhz clock used to create a 25 mhz clock to use in vga snchronization . then a simple window is created on the screen -SPARTA
alu-4bit
- alu包含各种运算功能，有点事现对于其他的程序，面积较小-it has a smaller square compared with othe program.
31-x-8-ROM-master
- Verilog module for a ROM. The rom needs to be able to hold 32 unsigned Integers each 8 Bits. Thus it must have32 address lines.
memory
- Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd- Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd