资源列表
add
- 自己用verilog写的加法器，时序仿真已经通过-Their own written with verilog adder, timing simulation has been adopted
UART
- uart串口通讯，串口初始化，串口接收数据，串口发送数据-uart serial communication, serial port initialization, the serial port receive data, send data to serial
8051_hex_dec_conv
- 8051 Assembler. hex to dec conversions.
easy_vhdl
- 一些常用的VHDL代码，包括逻辑门，寄存器，译码器，数据选择器，触发器- Some common VHDL code, including logic gates, register, decoder, data selector, trigger, etc.
Viterbi_Decoder
- viterbi decoder for convolution encoder
round_robin_vhdl
- Round Robin using VHDL
46_generic
- VHDL中generic缺省值的使用 -failed to translate
md
- 基于VHDL语言实现的曼彻斯特解码。 -VHDL manchester decode
red-and-green
- 红绿灯代码，根据两条交叉路绿灯时测得的流量，比较大小后实时改变红绿灯时间，最多增减20秒。-Traffic light code, when the green light under the two measured cross-road traffic, more traffic lights to change the size of the time immediately after the maximum change in 20 seconds.
AD9850
- DDS直接数字频率合成AD9850源代码，能输出0到40M分辨率为1K的正弦波形。-DDS Direct Digital Synthesizer AD9850 source code, can output a resolution of 0 to 40M 1K sine wave.
FPGA-based-16X16-dot-matrix
- 基于FPGA的16X16点阵去显示汉字，让汉字滚动显示-FPGA-based 16X16 dot matrix to display Chinese characters
correlator
- 代码主要说明了乘积检波器的vhdl描述，同时压缩包中还附带的与之相关的rom,mul4*4乘法器的vhdl描述。 用quartus2软件即可打开使用。-Code shows the main detectors of vhdl product descr iptions, at the same time compressed package also comes with associated rom, mul4* 4 multiplier vhdl descr iption. Quart