资源列表
VHDL
- 电子设计自动化软件下的3-8位译码器，触发器的VHDL 代码-Electronic design automation software under the 3-8 bit decoder, triggers the VHDL code
1
- 一个VHDL实现的测频计 LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY freq IS PORT( Fsignal : IN std_logic -- Rst : IN std_logic Gate : IN std_logic Ready : OUT std_lo
spi_interface_premier_slave
- verilog版的spi接口的slaver部分程序-verilog version of the spi interface slaver part of the program
light
- 基于verilog语言的交通控制灯的源代码-Traffic control lights based on verilog
main
- 篮球24秒计时程序，用于篮球比赛快结束时的倒计时-24 seconds counting for basketball game
1553encoder
- 1553曼彻斯特编码的verilog代码 -1553 Manchester coding verilog code
rgb2ycbcr
- color space transformation with input coeficient
decdor_38
- 用VHDL编的编码器,具有多种功能,希望呢温暖感跟大家共享~!-VHDL addendum to the encoder, with a variety of functions and warm sense of hope do share with you ~!
lcd.rar
- Nios II驱动ocmj4X8c液晶的程序 时钟50M,Nios II-driven process ocmj4X8c LCD clock 50M
countor
- This code for countor . it is design in verilog HDL.
VGA_FPGA
- 基于FPGA的VGA控制器，可在屏幕显示彩色条纹-A vga controller based on FPGA
CIC.rar
- cpld/fpga积分梳状滤波器(CIC)设计,cpld/fpga Integral comb filter (CIC) design