资源列表
compare
- 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
spi
- 用verilog实现spi接口的简单小程序，适合初学者学习。-Use verilog implementation of spi interface simple small program, suitable for beginners to learn.
clock
- 用verilog实现数字时钟，测试过基本上满足要求，适合初学者学习-Use verilog digital clock
fifo
- 异步FIFO的实现，很经典的三段式状态机的写法。-The realization of the asynchronous FIFO, very classic three-step writing state machine.
TSMC
- TCBN65LPBWP7T VERSION 200A tsmc CLN65LP : 65nm CMOS LOGIC Low Power
8-TFT_24
- 基于Xilinx Spartan6自制开发板实验，2.4存TFT屏静态刷新特定图片。如果要修改图片，请使用Matlab将图片生成*.coe格式，生成ROM加载。-Development board based on Xilinx Spartan6 homemade experiment, 2.4 TFT screen kept static refresh specific picture. If you want to modify the picture, the image is gene
RISC_CPU
- 毕业设计，基于Xilinx Spartan6自制开发板实验。毕业设计，能够实现简单的计算器。VHDDL-Graduation design, development board based on Xilinx Spartan6 homemade experiment. Graduation design, to achieve a simple calculator. VHDDL
11-songer
- 基于Xilinx Spartan6的FPGA案例 播放 梁祝 的程序 VHDL-Play Lovers of FPGA-based Xilinx Spartan6 case program VHDL
mu0
- 基于Xilinx Spartan6的 一个简单的CPU MU0 VHDL-Based on a simple CPU Xilinx Spartan6 of MU0 VHDL
1-flowingled
- 基于Xilinx Spartan6 简单的流水灯实验 VHDL -Based on Xilinx Spartan6 simple VHDL test water lights
demodul_2ASK_NonCoherent
- 2ASK 非 相 干 解 调, verilog编程实现-2ASK non-coherent demodulation, verilog realization
uart_mod
- 与上位机通信的串口驱动程序，基于VHDL语言-uart module