资源列表
Four-input-static-display
- 用Verilog语言写四位静态输入显示，可做课堂实验后课后作业，有完整代码-Written in Verilog language, according to the four static input to do homework after class experiment, has a complete code
Binary-BCD-code
- 用Verilog语言写的二进制转BCD码,可以作为课堂教学实验或者课后作业，有完整工程代码-Written in Verilog language transfer binary BCD code, can be used as a teaching experiment or the homework, a complete project code
8bits
- 用Verilog语言模拟的8位优先编码器，可作为课堂作业实用，是完整工程代码-Using Verilog language simulation of the 8 priority encoder, can be used as a classroom operation, is a complete code
TIMER
- 用Verilog语言模拟的数字时钟的功能，时分秒工能都有，适合做毕设，完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete
traffic
- 用Verilog语言模拟交通灯实验，内容简单，适合初学者，- Simulation of traffic light experiment using Verilog language
transmitter
- UART transmitter.v.zip
sswcsz3
- VHDL实现猜数字游戏，北邮数电实验，功能齐全，有伪随机-VHDL realization guessing game, BUPT number of electric experiment
dadishu_v1
- VHDL实现简单打地鼠游戏机，北邮数电实验-VHDL simple playing hamster games, BUPT number of electric experiment
LTC1407
- 针对ADC器件LTC1407的时序编写的Verilog程序，经过实际测试成功，简单实用-According to the timing of ADC device LTC1407, Verilog program, after the actual test success, simple and practical
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of
Piano_vhdl
- Here is the Piano code for FPGA(Basys 2) with switches.
DDR3-SDRAM-Verilog-Model
- 官方网站的verilog语言描写的ddr3 sdram仿真模型。各种型号可选。