资源列表
multiplexer
- How multiplexer is implemented using FPGA board is given here
adder_ckt
- This a source code for how adder is implemented in FPGA-This is a source code for how adder is implemented in FPGA
tristate_dr
- Hardware descr iption language for combinational circuit tristate driver how it is implemented
mealy_is
- How mealy finite state machine is implemented using VHDL
diffofsignalandvariable
- How signals and variables are declared and used in vhdl
hdlrecord
- Bluespec sample program and program for comparator. Cyclone 2 FPGA Real Time Clock program.
Op-Amp-Model(VHDL-AMS)
- 模拟信号模型-运算放大器模型Op Amp Model的VHDL-AMS程序-Analog signal model- op amp model Amp Model VHDL-AMS Op program
N-DtoA-VHDL-AMS
- 下面是一个混合信号的例子,是一个N位D/A转换器的VHDL-AMS描述-The following is an example of a mixed signal that is a N bit D/A converter described in VHDL-AMS
rcvr
- verilog的串口接收程序，有详细注释，适合学习-verilog serial port to receive the program, there are detailed notes, suitable for learning
fft1024-verilogCODE
- fft 1024点verilog代码,适用于基-4的FFT算法描述，使用quartus，modelsim，-fftpoint 1024 verilog code
an181_2_2
- Excalibur FPGA多主参考设计-Excalibur Solutions— Multi-Master Reference Design
uart_lcd_display_XUP
- Uart串口通信程序，PC机向FPGA的串口发送数据，FPGA的串口收到数据后回传到PC机，同时显示在lcd屏。-Uart serial communication program: The serial port of PC sends data to the FPGA. After the serial port of FPGA receives the data, FPGA sends the received data back to the PC, simultaneously dis