资源列表
fenpin5_5
- Verilog 语言实现利用FPGA对输入方波实现5.5分频-the frequency of a rectangular wave is divided 5.5 using the FPGA
VD_212_correction
- 对田耘等所著《无线通信FPGA设计》中第324页代码错误进行了更正，并对代码进行了注释。同时给出了测试激励文件。-Tian Yun and other book Wireless Communications FPGA design on page 324 of the code error has been corrected, and the code of the comments.At the same time gives the test bench files.
vedio_format
- 本代码是bt1120 格式产生以及转换为rgb源代码，开发环境为vhdl。-this code describe the bt1120 generator and change form soure code.
serial
- 此为Verilog写的功能测试函数，主要用于模块的测试，本程序已调试成功。-This is the function of test functions written in Verilog, mainly used in the test module, the program has been successful debugging.
mux
- verilog code it is about multiplexer
FPGAcode
- 函数，任务，有限状态机，状态机接口设计，SRAM设计FIFO的代码实现-Functions, tasks, finite state machine, the state machine interface design, SRAM FIFO design code implements
FPGAcode
- verilog HDL语言编程实现比较、分频、除法、阻塞与非阻塞语句的源文件和test文件-compare, division,half_clock,block and unblock
CLK_DIV_IP_packager
- Vivado IP packager的实例。Vivado版本2014.2，使用Verilog语言对一个分频程序打包。-Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.
ITU_656_Encoder
- ITU_656协议下的图像编程代码，适用于此协议下传输图像的开发者-The image programming code under the ITU_656 protocol, suitable for transmission of images to developers under this Agreement
Borax_BA5_SoC_Kit_Rev2
- 骏龙科技有限公司Borax开发板SoC_Kit的实例程序，适合此开发板的使用者-Cytech technology Borax development board SoC_Kit examples of procedures for the development board users
5CSXFC6D6F31C8N_pin_location
- 友晶科技公司开发板SOC-KIT的FPGA芯片5CSXFC6D6F31C8N的管脚分布，使用与此开发板的使用者-Pin Terasic company SOC-KIT development board FPGA chip 5CSXFC6D6F31C8N distribution, and use this development board users
PCIe_13.1
- 基于FPGA的pcie13.0的接口控制模块的下载执行程序，可以直接实现pcie13.0接口的控制-FPGA pcie13.0 interface control module download executable program based on direct control can achieve pcie13.0 interface