- bbbbbbbbbb 实现图象的亮度转换:每点击一次“增加亮度”
- article utility package which is helping you to write arabic numbers
- MyElectCourse 网络选课系统 文件包含数据库设计和具体代码
- sniffex Sniffer code in c you can use this on linux and get all packets sniffed its free source code
- yuzhi 采用三种不同算法求取二值化的阈值(双峰法
- CMOSdigitalIntegratedcircuitsbykang this book is for digital design
资源列表
Asy_slavefifo_rdwr(141027)
- FPGA 控制CY7C68013A芯片的收发程序,调试通过,最高速度18M-CY7C68013A chip transceiver FPGA control procedures, debugging through, the maximum speed of 18M
Lvbo
- 实现信号滤波,可根据外部信号毛刺干扰的特点改变滤波时钟来改变滤波宽度-Achieve signal filtering, the filter can be changed according to the characteristics of the external clock signal glitch to change the filter width
TLV5630ceshi
- TLV5630 DA转换芯片FPGA控制程序源代码,verilog编写-TLV5630 DA converter chip FPGA control program source code, verilog prepared
coordinate-transformation
- 实现坐标变换,包括clark和park变换,clark变换实现三相静止坐标转换到两相静止坐标,park变换实现两相静止坐标转换到两相旋转坐标-Achieve coordinate transformation, including clark and park transform, clarke transform phase static coordinate conversion to the two-phase stationary coordinate, park transform t
i2s_dome2
- 音频接口I2S的Verilog实现, -Audio port of Verilog
BTO
- 这是一个十六进制显示译码器,可在EDA板子上实现,希望对大家有帮助-This is a hexadecimal display decoder may be implemented on EDA board, we hope to help
mspi
- 通过SPI接口给一段位宽16位长度为8的配置寄存器进行赋值。这些配置寄存器均要求可读可写。并编写激励进行测试,先写后读,验证功能正确性。SPI接口电路的具体要求如下: (1)输入信号为全局复位信号reset,片选信号cs,串行输入时钟信号sclk,串行数据输入信号sdi和串行数据输出信号sdo。 (2)每个传输周期进行一次16位的数据传输。每个传输周期内共传输24比特的数据,其中最开始的两个比特为10时表示读操作,最开始的两个比特为11时表示写操作,接着6个比特表示地址信息,再接下来
hilbert_transformer_latest
- Hilbert Transform Core is very best for your projects.
cic_core
- CIC CORE is very good core for your projects.
Verilog-HDL-introduction
- 简单实用的Verilog HDL 入门教程-Verilog HDL introduction
Quartus13.0-create-NIOS2-
- Quartus13.0创建NIOS2实验步骤说明-Quartus13.0 create NIOS2 introduction
clip_viseo
- 视频旋转 连续写,离散读,为了提高效率,分块突发读写。-video rotate
