资源列表
Quartus-II-11.0.208-SP1-Altera-Complete-Design-Su
- Altera Quartus 12.1 Software Patch
Q12.1Crackx86
- Altera Quartus 12.1 Software Patch
Counter
- best simple counter for verilog modelsim6.5
anjianjuzhen
- 在Quartus II 环境下利用Verilog语言编写的按键矩阵和位移同化程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language assimilation key matrix and displacement procedures, including modular devices and simulation waveforms
shizhong
- 在Quartus II 环境下利用Verilog语言编写的时钟程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language clock procedures, including modular devices and simulation waveforms
miaobiao
- 在Quartus II 环境下利用Verilog语言编写的秒表程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language stopwatch procedures, including modular devices and simulation waveforms
traffic_control2
- 交通红绿灯管理系统。用一片HDPLD和若干外围电路实现十字路*通管理器。该管理器控制甲乙两道的的红黄绿三色灯，指挥车辆和行人安全通行。该交通管理器是由控制器和受其控制的三个定时器及六个交通管理灯组成。-Circuit crossroads traffic manager. The manager controls the B two red-yellow-green lights, directing vehicles and pedestrians safe passage. The Tra
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path
TCD1304_drive
- FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机-FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial
mimo_dectection20160112
- mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过-mimo detection algorithms on FPGA, including a minimum zero forcing detection algorithm and ML detection algorithm has been through in the ISE simulation
HDB3
- FPGA实验_HDB3编码器设计(包含5个模块)-FPGA design experiments _HDB3 encoder (including 5 modules)
FPGA_BDPSK
- FPGA实验_BDPSK调制解调器设计(包含10个模块)-Experimental _BDPSK modem FPGA design (including 10 modules)