资源列表
uart_loopback
- uart loopback and test bench .
Uart_to_bus
- The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode commands are designed to be used wi
tp-vhdl
- compteur digital VHDL 1ERE VERSION
L-CLA20_20-code.
- DHL CLA20_20 development with the Verilog bit ahead carry adder code.
rapport_vhdl
- Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone -Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone II
Lcd_800_480
- 基于DE2-70开发板的FPGA和NIOS系统设计的LCD（800-480）液晶显示控制系统的程序设计。-DE2-70 FPGA-based development board and the NIOS system design LCD (800-480) LCD control system programming.
dds
- 这是一个基于ＦＰＧＡ设计的ＤＤＳ信号发生器设计。能够生成正弦波＼ＡＳＫ＼ＰＳＫ＼ＡＭ＼ＦＭ等波形。-This is an FPGA design of DDS signal generator based on. Capable of generating sine \ASK\PSK\AM\FM and other waveforms.
QPSK
- modelsim环境下QPSK解调电路的仿真-modelsim simulation environment under QPSK demodulation circuit
AES_core
- 蓝牙AES编码，希望对深入了解蓝牙开发的人有帮助-Bluetooth AES coding, and I hope people understand Bluetooth development help
add_sin
- 使用quartus软件编写VHDL语言一个累加器程序-Quartus software using VHDL language to write a program accumulator
comp8_1
- 使用quartus软件编写VHDL语言一个比较器程序-Quartus software using VHDL language to write a program comparator
lzp
- 用Quartus生成一个10KHZ的正弦波-10KHZ generate a sine wave with Quartus