资源列表
YCbCr2RGB
- 浮点数算法 ycbcr格式转换成rgb格式-float convert ycbcr to rgb
2point_data
- 基于Quatusii的两点非均匀性校正的VHDL程序，用于红外图像的预处理-Quatusii based on two non-uniformity correction in the VHDL program for infrared image preprocessing
VHDL_study
- vhdl实用教程，经典教程，本书特意做了书签，方便初学者查询-vhdl practical course, classic tutorial, the book deliberately made bookmarks, easy for beginners query
LM3SUARTSENDFIFO
- LM3S系列UART例程：发送FIFO触发中断原理-LM3S Series UART routines: Send principle of FIFO trigger interrupt
Signed-Arithmetic-in-Verilog-2001
- 有符号数的完整讲义和例子Verilog 2001-Signed Arithmetic in Verilog 2001, paper with examples
config_ad9957
- 用Verilog正确配置ad9957，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad9957,, compiled in the ISE environment and realization of the right
LED
- LED跑马灯 代码为Verilog。已经在V5 ML506上验证过。 -LED Marquee code for Verilog. On the V5 ML506 has been verified.
debussy
- Debussy 是NOVAS Software, Inc(思源科技)发展的HDL Debug & Analysis tool，这套软体主要不是用来跑模拟或看波形，它最强大的功能是：能够在HDL source code、schematic diagram、waveform、state bubble diagram之间，即时做trace，协助工程师debug。 本文主要是介绍Debussy的使用，以及如何在Modelsim环境下生成Debussy所需要的fsdb文件-user guide f
init9956
- 基于AD9956的频率合成器的FPGA程序编程-AD9956 a FPGA Program
Crack_Altera_6[1][1].0-9.1
- quartus版本的破解 从6.1至9.0间所有版本-quartus crack version from 6.1 to 9.0 all versions
SATA_Verification_IP-SystemVerilog
- SATA Verification IP - SystemVerilog,是使用FPGA做的sata接口部分，是一篇文档-SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
USB2.0-IP-core
- 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help