资源列表
vga2
- 一个简单的小球挡板游戏，通过VGA接口可在显示屏上显示，支持双人对战-A simple ball game baffle, through VGA interface can be displayed on the display screen, supports double play
VGA3
- 用verilog语言实现弹球屏保，静态图片显示，动态显示ISE代码-ISE verilog
digitron
- 数码管显示工程，里面包含了译码器等多用电路的VHDL源码和顶层电路图，并最后进行了组合。-Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
digitron
- 数码管显示，里面包含了译码器等多用电路的源码和顶层电路图，并最后进行了组合。-Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
addafilter
- 基于NIOSii的数字滤波器，包括AD和DA的读取输出部分，包括C语言源码和verilog源工程-digital filter based on Nios2
cnt63dis
- ISE环境下Verilog编程实现63进制计数器并用7段译码显像管显示-ISE Verilog programming environment under 63 binary counter with 7 segment decoder CRT display
coubter_key
- ISE环境下Verilog编程实现机械按键去抖-ISE Verilog programming environment under mechanical debounces
counter6display
- ISE环境下Verilog变成实现六位计数器并用7段显像管显示-ISE Verilog environment becomes realized under six counter with 7-segment display CRT
squa
- Verilog语言ISE下实现方波产生和占空比调节-ISE Verilog language implementations under wave generator
absolute2relative_coding
- ISE编程仿真DPSK中相对码和绝对码的转换-DPSK code conversion relative and absolute code
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
ug871_vivad_HLS_tutorial
- Xilinx Vivado HLS 高层次综合工具的软件使用说明-Vivado HLS Xilinx high level integrated tool for the use of software instructions