资源列表
ledyyw
- 用VHDL实现流水灯，配置管脚，并在FPGA板上得到实现-VHDL implementation of water with the lights, configuration pins, and realized in FPGA board
SRAM--verilogsram
- 在quatus2环境下编写的SRAM读写实验,verilog代码-Environment written in quatus2 SRAM read and write test, verilog code
exp1.5_mux8_1
- 用VHDL及verylog语言设计一个8选一数据选择器，可以在Quartus II中仿真-Language Design with VHDL and verylog a 8-to-one data selector, you can simulate in the Quartus II
AD8522_SPI
- AD8522模拟数字转换芯片sdi接口配置代码-AD8522 analog-digital converter chip sdi interface configuration code
ym138
- 这是一个使用VHDL语言编写的138译码器，至于138译码器的功能在此就不赘述了。-This is a 138 using the VHDL language decoder, decoder 138 function as this will not go into details.
adc_top
- AD9480驱动与接口verilog代码-AD9480 driver and interface verilog code
DE2_SD_Card_Audio
- DE2板上读取SD卡，使用nios ii IDE开发环境，可以读取SD卡里面的任何文件系统。-Read SD Card based on the DE2 board,the environment is nios ii IDE
verilog1
- 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed pac
RS-decoder
- RS 解码器主要包括以下5 个主要部分：伴随式计算、计算错误位置和错误值多项式、 钱搜索计算错误位置、福尼算法计算错误值和纠正解码输出。-RS decoder includes the following five main parts: With style, calculated error location and error value polynomial, Calculated error location search of money
fpgaad7865
- 用FPGA控制AD7865的控制逻辑，状态机-AD7865 control logic
EP2C8Q_Nios_TFT_LCD
- EP2C8Q，利用nios驱动2.4寸TFT屏-EP2C8Q，use nios to let 2.4_tft screen work normal
I2C
- I2C 接口的verilog实现源代码，-source of I2C inteference using verilog