资源列表
FIRde-verilog-shixian
- 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
freq_div
- 用verilog实现基于fpga的通用分频器，-Divider using verilog achieve common
eros
- 俄罗斯方块程序。-FPGA development board schematics
fifo_vhdl
- 基于vhdl语言实现的fifo控制器。经过仿真及实际测试-failed to translate
shizihong
- 用VHDL语言编写数字钟的程序，实现数字钟的几个功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
EDACLOCK
- 用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
EP2C8_PER_VGA
- VGA的驱动程序，DE2的例程，适用于初学者了解VGA的操作!-VGA driver, DE2 routine
PC_WR_EEPROM
- 利用altera公司的FPGA使用verilog语言实现对EEPROM的读和写的功能 利用串口发送数据-Altera FPGA verilog language to achieve the serial port to send data to the EEPROM read and write
FPGA_DDR-SDRAM
- FPGA对SDRAM的控制，有部分源码，-FPGA SDRAM control, part of the source,...
DES.zip
- DES 加密算法的实现，使用硬件描述语言VHDL编写,DES encryption algorithm realization, uses hardware descr iption language VHDL to compile
CIC.rar
- cpld/fpga积分梳状滤波器(CIC)设计,cpld/fpga Integral comb filter (CIC) design
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code