资源列表
CPU_16bit
- 一个五段流水的16位cpu vhdl源码，可综合也可仿真(A five section of the 16 bit CPU VHDL source code, can be integrated can also be simulated)
DE1_SoC_Audio
- 声音录制、播放的Verilog代码，用于Altera Cyclone V SOC. 写时适配的是DE1-SOC开发板。-Audio recording and playing code for Altera Cyclone V SOC FPGA. Code was designed for DE1-SOC development board, but could be reference for other boards.
UART_test
- EP2S90 进行RS232 通信的一种高效率算法的程序-An efficient algorithm for EP2S90 RS232 communication procedures
dds6_ise12migration
- 以DE2为开发平台，采用Veriolg语言编程，实现了DDS信号输出，频率，步进，波形输出均可调，采用Modelsim以及FPGA内嵌逻辑分析仪验证设计的正确性，可以满足一定的工程需求。(With DE2 as the development platform and Veriolg language programming, the DDS signal output, frequency, step and waveform output can be adjusted. The corre
vga_dis_module
- VGA接口通信程序，欢迎大家下载交流！使用时需要修改对应引脚~-VGA interface communication program, are welcome to download the exchange! Need to be modified when using the corresponding pin ~
FPFA-DSP
- FPGA可以实现DSP算法，本材料提供了详细的实现方法，对原理与实现给出清晰的思路，是FPGA开发参考的好资料。-FPGA can implement DSP algorithms, this material provides a detailed implementation methods, theory and implementation gives a clear idea is a good reference information on FPGA development.
uart
- 用verilog语言编写的串口读写程序，波特率可调，亲测可用。-this is a program for UART by verilog, which is useful.
main
- 嵌入式系统加密的FPGA实现源码，可直接用于工程(Embedded system encryption FPGA implementation source code, can be used directly for the project)
S05_example_Network
- vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)
signal_gaojindu
- 信号源的verilog代码,已经调试通过，很有参考价值-verilog code of signal source
EDA_clock1
- 电子秒表电路，可在开发版上下载运行，verlog开发-electronic stopwatch circuit may download the development version running verlog Development
EX4-DA_TLC5615
- 主要实现AD转换模块的驱动，包括AD的测试模块。-The main driver to achieve AD conversion module, including AD test modules