资源列表
vga_cd
- 用verilog编写计数程序，在VGA上显示的，适合VGA的初学者。测试平台DE0 。-Counting program written in verilog, displayed on the VGA, VGA suitable for beginners. Test platform DE0.
IDT7005
- 双端口静态RAM的VHDL程序，具体芯片型号为IDT7005-DUAL-PORT STATIC RAM
ethernet
- 在xilinx用verilog实现工业以太网的全部文件-industrial ethernet in xilinx
zy4668_music
- 本源码实现了用VHDL语言设计音乐播放器-This source code implements the design using VHDL language music player
buzzer_piano
- 实现一个简单的钢琴功能。按下按键K1~K6，BUZZER分别发出DO、RE、ME、FA、SO、LA六个音符。-To achieve a simple piano function. Press the keys K1 ~ K6, BUZZER issued DO, RE, ME, FA, SO, LA six notes.
shudianshiyan
- 数字电路与逻辑设计实验编程，包含多功能电子钟程序，实用，简易-Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple
O_DDS_PHASE
- 包括了DDS设计的全部源码，其中相位和频率均可调，可直接应用于sopc/fpga设计中-DDS design includes all the source code, which can be adjusted for phase and frequency can be directly applied to sopc/fpga design
color_vga.tar
- VGA DIsplay control. which reads pixel data stored in coregen on fpga and displays image on monitor using VGA
taxivalue
- 我用FPGA来实现，这是一个出租车计价器，用来计算里程，我已在Quartus 2实现。-I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.
verilog
- 各种基础的Verilog hdl实验的实验报告，包括D触发器，移位寄存器，选择器，译码器等等，有很详细的操作步骤，对于初学者很有用。-All based on Verilog hdl experiments are reported, including the D flip-flops, shift registers, selectors, decoders, etc., there are detailed steps, useful for beginners.
jtag_uart
- jtag_uart实现FPGA内部和计算机之间的通信，实时监控方便-jtag_uart achieve FPGA communication between the internal and the computer, real-time monitoring convenience
SDRAM
- 非常简单好用的SDRAM控制器，使初学者更加容易理解SDRAM的控制的操作，在Quatrtus环境中验证没问题。-SDRAM controller is very simple and easy to make it easier for beginners to understand the operation of the control of SDRAM, the environment in Quatrtus verify no problem.