资源列表
music
- 利用PWM使蜂鸣器产生音乐的verilog源代码及《友谊地久天长》的电路设计-Generates a PWM buzzer music verilog source code and Auld Lang Syne circuit design
scr
- 八路抢答器，包括按键检测，计时，LED显示，蜂鸣器驱动。-8—way responder
serial-and-parallel-convert
- 8bit串行数据转换为8bit并行数据，8bit并行数据转换为8bit串行数据，代码注释完整。-serial and parallel convert
DDS
- DDS函数信号发生器，这是我在xilinx平台上实现的，可以产生不同频率，不同函数形式的函数信号。如三角波，方波等-DDS function generator, this is my on xilinx platform, can produce the function of different frequency signals.
DataPath
- datapath-datapath of Cpu
Verilog
- 这是 夏宇闻Verilog数字系统设计教程中部分例程代码，适合初学Verilog的人-This is Xia Yu smell Verilog digital system design tutorial part of the routine code, suitable for beginners of Verilog
testbench
- testbench for Carry look ahead adder
RCA
- ripple carry adder vhdl code
fast-Cla
- fast Carry look ahead adder
CSA
- carry save adder vhdl
wisbone_2_ahb.tar
- ARM Bus Interface RTL Reference Code
LCD12864
- VHDL编写的LCD12864控制程序，是开发板上带的，绝对正确。本人验证过。希望对学习这方面的朋友有用。-VHDL LCD12864 control procedures, the development board with the absolute right. I have verified. I hope to learn this aspect of the useful friends.