资源列表
adder8
- 8位加法器源代码，vivado实现编写。-8 adder Source, vivado achieve write.
Slides-of-VHDL
- VHDL课件，包括Xilinx软件的入门使用，VHDL基本语法，状态机以及其他。-VHDL courseware, including entry using Xilinx software, VHDL basic grammar, state machines, and others.
ball_vhdl
- 基于vhdl编写的两个弹球游戏合集，可实现弹球的弹性碰撞-Two pinball game collection based on VHDL written
keyboard_scan_XUP
- 数字密码锁，数字密码由4*3键盘输入，密码输入正确时，lcd屏上显示正确的密码，并显示OK；密码输入错误时，lcd屏上显示ERROR。-Digital lock, numeric password is scanned the 4* 3 keypad, when you enter the correct password, lcd screen displays the correct password and OK when you enter the wrong password, t
snake_VHDL
- 基于vhdl编写的贪吃蛇游戏，课程设计必备-Based on the VHDL language of the snake game, curriculum design essential
Timer_design_XUP
- verilog写的秒计数器，计数结果显示在四个七段四个数码管上，两个作为秒位，两个作为分钟位。-A seconds counter described by verilog, counting results are displayed on the four seven four digital tube, two as second bit, two as a minute bit.
clk-10divide
- 基于verilog编写的十分频时钟，简单易懂，欢迎大家下载和学习-Based on the frequency counter verilog prepared very easy to understand, are welcome to download and learn
clk-divide5
- 实现5分频计数的veriog电路，简单易懂，欢迎大家下载学习-Achieve 5 divider count veriog circuit, easy to understand, welcome to download the study
counter
- 实在在开发板上显示的摸60计数器，时钟分频为1s，能在数码管上显示-Development board really feel 60 counter display, the clock frequency of 1s, can be displayed on the digital tube
DD
- This file is the VHDL code for controlling the stepping motor. The clock driving the stepping motor driver module. through signal it can control the direction of the stepping motor.-This file is the VHDL code for controlling the stepping motor. The c
shujujiance
- 单进程Mealy型数据监测。实现100101的数据监测，可实现多次组合监测，更改移植方便简单。-Mealy-type single-process data monitoring. Achieve 100,101 data monitoring, enabling multiple portfolio monitoring, change transplantation convenient and simple.
yiweijicunqi
- 使用并置“&”法写出通用移位寄存器的VHDL模型。在时钟控制下将输入数据寄存，在满足输出条件时输出数据。-Use and set & method common shift register to write VHDL models. Under clock control the input data registers, the output data in the output condition is satisfied.