资源列表
altpllpll
- MP3 player for nios -MP3 nios HW priject
Recv
- 运用VHDL语言，实现串口的接收子程序，可以将该子模块加载到主程序中。-VHDL UART RECEIVE
triangular_vhd
- This the triangular wave generation vhdl code to check the wave form in modelsim simulator-This is the triangular wave generation vhdl code to check the wave form in modelsim simulator
hdb3
- 实现通信过程中的hdb3转换,是通信原理课程中很重要的部分.
add.rar
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）,Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
crc
- crc project by vhdl -crc project by vhdl ..............
vga1
- VGA 接口模块，800*600接口时序verilog实现-VGA interface module, 800* 600 interface timing verilog implementation
i2c_slave
- i2c slave 代码，可综合，通过fpga验证-i2c slave code
VGA_CON
- 超帅VGA控制器源码 ，绝对原创 超帅VGA控制器源码 ，绝对原创-The VGA controller source code, Chaoshuai absolute originality
codic
- 8级cordic 算法verilog-8 cordic algorithm verilog
Conversion
- pipeline test in verilog
int_osc
- CPLD的内部振荡器的应用，内部振荡器是位于用户闪存模块中的 4.4-MHz( 典型输出 ) 时钟源。采用内部振荡器不但减少了元件数量，而且还能够降低系统功耗。-The application of the internal CPLD oscillator, internal oscillator is located in flash memory module of the user 4.4 MHz (typical output) clock source the inside oscil