资源列表
vhdl
- 此程序为VHDL的四位比较器，两位输入，三位输出-This procedure the VHDL four comparators, two input, three output
jiaotongxinhao
- vhdl语言编写的，在QuartusII下，交通信号灯控制器-vhdl language, in QuartusII, the traffic signal controller
rgb_to_ycbcr
- rgb 转 ycrcb verilog 语言-rgb to ycrcb
CANDY1
- 用VHDL实现的数字钟，实现消抖，计时，显示分秒，秒表等功能-VHDL implementation with digital clock and realize elimination shake, timing, displays minutes and seconds, stopwatch functions
uartTransceiver
- Verilog Serial port
U_XMIT
- 8位并行转穿行发送程序，波特率可自行设置，经检验有实用效果-8-bit parallel transfer walk through the sending program, the baud rate can be set up their own practical effect inspection
pcm_unlock_rdreg_prog
- 在NEXYS3开发板上，对于PCM的写操作时序-the time of programming PCM on NEXYS3
Asynchronous
- 异步加法计数器，采用D触发器实现的二进制计数器-Asynchronous adding counter using D flip-flop to achieve binary counter
LCD
- VHDL LCD Interface Code
Multiplier
- verilog implementation of the 32bit multiplier
dwt
- 基于 verilog的卷积运算代码，应用于离散小波分析。-verilog conv
LCD_1602
- verilog语言写的1602显示，已经测试成功-verilog language written in 1602 show