资源列表
verilog_Manchester
- 曼彻斯特码编码电路，在工业电路中有较好的抗干扰性，而且编码电路简单，容易在FPGA上实现-Manchester encoding circuit, the circuit in the industry in a better anti-interference, and the coding circuit is simple, easily implemented on FPGA
dac
- DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog-DA-chip SPI protocol output control does not read write-only FPGA with verilog
AD_fsm
- AD7892的状态机VHDL代码。完成时序控制，4通道数据采集和AD转换。-the FSM of AD7892
rxpart
- uart异步串口收模块，将串口数据进行组合变成8位的字节。波特率可自行调节-uart receive asynchronous serial module, serial data will be combined to become 8 bytes. The baud rate of self-regulation
sineROM
- 自己写得一个关于sine（32X24）的程序-own written on a sine (32X24) procedures
lkmusic
- 基于spartan3火龙刀系列FPGA开发板制作的音乐发生器实验例程
modelsim7.2license
- 用于modelsim7.2的破解，里面有详细说明，很有用-For the crack modelsim7.2, which has detailed instructions, very useful
fft_16
- 基于FPGA用verilog语言实现16点FFT-16-point FFT FPGA-based verilog language
wishbone_to_avalon
- wishbone-slave-and-master-to-avalon-bus,是关于wishbone总线和Avalon总线的转换，有实用价值，采用的是verilog编写
costas
- costas锁相环matlab仿真代码，对costas环的研究和硬件实现具有指导意义。-Costas Phase-Loop MATLAB Code.
UART_Send_handle
- 这是一个很好的基于verilog的串口通信422模块，已经经过多次验证，绝对可靠，可直接使用，本人已在工程中多次使用，无误差-This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly used in the project, no error
lift.vhd
- 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically dete