资源列表
i2c_master_byte_ctrl
- I2C控制总线按照word写，用verilog实现的主机写功能-I2C control bus according to the word write and write functions implemented by host verilog
fpgaad7865
- 用FPGA控制AD7865的控制逻辑，状态机-AD7865 control logic
PC8501
- 本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
fast_antilog_latest.tar
- Anti-Logarithm (square-root), base-2, single-cycle
UART
- Verilog编写的UART模块,波特率19200，系统时钟100MHz,x3s50an应用成功-UART module using Verilog
Relay-control
- 该代码是继电器控制的汇编程序，在简单的单片机最小系统上即可实现对继电器的控制-This code is relay control assembly program, in simple single chip minimize system to relay of the control can be realized
ahb_master
- ahb master 文件，主要是ahb发数据-ahb master file
DSP
- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001
PCNN FPGA
- 用VHDL语言写的PCNN一个神经元的工作机制
adder_4bit
- 四位加法器，用OrCAD完成，可用于八位乃至十六位加法器的设计原型-four adder with OrCAD completed, can be used for eight or even 16 Adder design prototype
xcymain
- NIOS2软核嵌入式代码实现对电机的测控-NIOS2 soft-core embedded code monitoring and control of the motor
Division
- Verilog hdl 除法综合仿真实现，另包含测试文件-Verilog hdl Division