资源列表
mytest
- Pluto receives data from the PC serial port, de-serializes it, and send it to the LCD module. The de-serializer is the same module from the serial interface project, so it is just instantiated here.
code1
- 实现50MHz时钟分频，点亮fpga开发板的led灯，并且让数码管动态显示电子计时-Implementation of 50MHz clock frequency, the LED lights FPGA development board, and make digital tube dynamic display of electronic timing
HDLC协议接收文件
- HDLC协议接收文件，vhdl版本，适用于HDLC通讯协议
automachine
- 自动售货机 l 设计要求： 1．机器有一个投币孔，每次只能投入一枚硬币，但可以连续投入多枚硬币。机器能识别的硬币金额为1元，5角和1角。顾客可选择的饮料价格有1元，1元5角，2元三种。每次只能售出1瓶饮料。 2．购买饮料时先选择饮料价格再投币，当投入的硬币总金额达到或超过饮料价格后，机器发出指示信号并拒收继续投入的硬币。顾客投币后，按动确定键，机器将发出饮料和找零硬币，若所投金额不足，则发出欠资信号指示。在欠资情况下，顾客可以继续投币购买，也可按取消键，机器将退出所投入的全部金额。
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
chengfaqi4
- 用VHDL实现四位乘法器，不直接用乘法实现，一来节省资源，二来可提高速度！-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
server
- This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
Four-multipliers-with-VHDL-
- 用VHDL实现四位乘法器，不直接用乘法实现。该代码思路清晰，希望可以帮助到大家！-Four multipliers with VHDL implementation, not directly with the multiplication implementation. The code is clear thinking, I hope to help to you!
zuhe
- 这个是12位的除法器，进过验证的，verilog程序，应用组合逻辑，欢迎下载-This is 12-bit divider, been to verification, verilog, application logic combinations are welcome to download
sv
- stack and events in system verilog
clock
- 多功能数字钟，VHDL语言编写；是EDA学习中常见问题-CLOCK
seg4_to_7
- 7段数码管译码器，在quartus里面实现，4为二进制数转换为7段数码管显示方式的二进制数-7 digital control decoder, which achieved in quartus, 4 for the binary number is converted to 7-segment digital display means of a binary number