资源列表
cordic
- 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
module
- 自己平时写的几个简单的模块，可以参考一下-He usually wrote a few simple modules, you can refer to
router_fifo
- 自己写的一个片上网络路由节点的fifo模块，工作频率达到1ghz。-Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
jedec
- component vhdl descr iption
async_receiver
- verilog语言，RS232异步接收和发送模块-verilog language, RS232 asynchronous receive and transmit modules
UART8_Receiver
- 自己编写的带有FIFO的UART串口接收模块，代码通过状态机实现-I have written to the FIFO UART serial receiver module code by the state machine.
ALU
- Verilog编写的ALU，可实现数学、移位、逻辑运算-ALU Verilog prepared, enabling mathematics, shift, logical operations
a8215
- 通过用FPGA的 VDHL语言 来实现8251的异步功能
counter
- counter in vhdl ... best fit
softdrink
- 饮料自动投币售卖机核心控制电路，功能包括开始操作，取消操作，找零，用Verilog实现-Automatic beverage vending machines coin core control circuit functions include start operation, cancel the operation, give change, achieved using Verilog
pcm
- ２４选８多路选择计数器 PCM编解码,采编器VHDL 源代码，包括顶层文件。-PCM(Pule code modulation) code and decoder
syn_fifo_style_2
- 由verilog实现的，异步FIFO，分为多模块实现。-Verilog achieved by the asynchronous FIFO, divided into multiple modules.