资源列表
mi
- I2C的状态机写法，改了好多次了，辛苦啊~~VHDL的-I2C state machine wording, changed many times
FPGA_TOP_ForYaoQi
- 分频器：利用计数来实现25M分频成10M的时钟，并且在开发板上利用LED实现跑马灯。-Divider: the use of the count clock frequency into 10M 25M points, and in the development of on-board LED to achieve the Marquee.
LCD-with-comment
- Simple code to display using 8051 interfacing with LCD 2x16
top_8b_10b_code
- 光纤通信8B_10b编码；8B/10B 编码顾名思义，即将发送方的 8bit 并行信号通过特殊的映射变成 10bit 并行信 号
LowPass
- A low-pass filter is a filter that passes low-frequency signals but attenuates (reduces the amplitude of) signals with frequencies higher than the cutoff frequency. The actual amount of attenuation for each frequency varies from filter to filter. It
defuzzification
- cher la MPPT d un panneau photovoltaï que -chercher la MPPT d un panneau photovoltaï que
FLASH_program
- 这是一个FPGA控制flash的一个编程代码，使用verilog语言，flash型号是k9k4G08U0-This is a flash of a FPGA control programming code, using verilog language, flash model is k9k4G08U0
HDB3_decoder
- 用VerilogHDL实现了HDB3码到NRZ码的解码过程-decode HDB3 code to NRZ code using VerilogHDL
traffic
- 本程序模拟路口的红黄绿交通灯的变化过程，用LED灯表示交通灯，并在数码管上显示当前状态剩余时间。 -- 红灯持续时间为30秒，黄灯3秒，绿灯30秒-This procedure simulated the red yellow and green traffic lights at the junction of the change process, said the traffic lights with LED lights, and digital tube displays the
counter_interleaver
- It is verilog based implementation of interleaver and counter for 0,15,3,7,8,4,2,14
duogongnengshuzizhong
- 多功能数字钟VHDL源文件,采用动态显示方式,6个数码管-Multifunction digital clock VHDL source files, dynamic display, six digital tube
init_LCD
- Initializes Toppoly TD043MTEA1 LCD. R02: Type 1 Dot inversion, VD and HD low polarity, Latch data on falling edge, 800x480RGB R03: Software register standby, pre-charge enabled, 100 drive capacity, PWM enabled, VGL pump enabled, cp_clk enabled, n