资源列表
EG7014_v1.0
- 用于fpga对EG7014液晶屏的刷新显示。avalone接口。-For the FPGA on the EG7014 LCD display refresh. avalone interface.
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
C
- C语言基本代码，计算点乘相加的和，打印星号图形，还有税收计算，代码比较精简，符合初学者的水平-C language code base, calculated by adding together and, more streamlined code, in line with the beginner level
lpc_ctrl
- LPC协议功能实现模块，能够完成读，写等操作-lpc control module
ketflink_fsm
- VERILOG的按键去抖，采用状态机的实现方法-VERILOG shaking the keys to using a state machine implementation
router_fifo
- 自己写的一个片上网络路由节点的fifo模块，工作频率达到1ghz。-Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
AD9851-for-MSP430
- AD9851是AD公司DDS芯片，可产生方波正弦波，这个是MSP430上移植的程序-AD9851 DDS chip is AD' s, can produce a square wave sine wave, this is the MSP430 on the transplant program
max197
- 基于NIOS II的MAX197多通道AD的程序，使用C语言编写-Based on NIOS II MAX197 multi-channel AD procedures, using C language to write
Timers
- vhdl code for Timers in 8051
cpu_1
- 用verilog设计五级CPU的框架，需要自己另行补充指令，可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
verilog实现ALU的源代码
- verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
ram128
- This 128 point code written in verilog-This is 128 point code written in verilog