资源列表
EDAshuzishizhong
- EDA秒表的制作及其源代码 有兴趣的 可以-EDA stopwatch production and its source code are interested can look at
alu
- verilog编写的alu模块-Verilog modules prepared by the ALU
unishift
- An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
i2c_wreg
- i2c 功能写操作源代码，供大家参考一下，软件上已经编译OK-i2c write function of the source code for your reference, the software has been compiled OK
frequency-divider
- anything frequency divider-frequency divider
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
Read_SPI_ADC
- This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.-This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 AD
vhdl3
- 两个例子提醒我们如果我们要使用锁存器则不需要任何操作，如果我们想避免锁存器的话，我们要让这个元器件的每一个可能条件赋予一个值-signal or variable "<name>" may not be assigned a new value in every possible path through the Process Statement
comm
- 串口通信电路VHDL描述，采用ISE环境开发-VHDL descr iption of serial communication circuits
FloatingPointMultiplier
- Implementation of 32-bits Floating Point Multiplier, based on IEEE 754 Standard
counter_3
- 三种计数器的verilog实现,二进制计数器,格雷码计数器,约翰逊计数器.初学硬件描述语言可参考。-Three kinds of counter verilog implementation of a binary counter, gray code counter, Johnson counter beginner hardware descr iption language can refer to