资源列表
resource2.v
- verilog描述寄存组合电路 很不错
traffic_1112
- 一个交通灯的vhdl语言实现 用 ＶＣ的 １．在指定的文件夹内查找某个文件 ２．获取系统文件夹的路径， 要求显示windows system temp 当前目录的路径 Ｃ语言 跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案 １ ６ １５ １０ ２１ １４ ９ ２０ ５ １６ １９ ２ ７ ２２ １１ ８ １３ ２４ １７ ４ ２５ １８ ３ １２
distributed_implementation
- VHDL 实现 有限冲击响应滤波器的设计（分布式）-VHDL realization of finite impulse response filter design (distributed)
structuralbehaviouraldecodervhdl
- A structural and behavioral modeling of a decoder
YCbCr2RGB_O
- 此代码是把YUV转成RGB的Verilog程序，多谢下载-This code is to convert RGB to YUV Verilog program, thank you download
fsm
- 状态机，描述五个不同状态的触发条件，运用流水线技术-State machine, described five different states of the trigger conditions, the use of pipelining
haming-code
- 4to16 decoder with 3to8 decoder verilog code-4to16 decoder with 3to8 decoder verilog code!!
COSTAS_LOOP
- 使用ISE12.1编写的Costas环，用于载波恢复，直接使用了IP核中的FIR和DDS模块-Use ISE12.1 written Costas loop for carrier recovery, the direct use of the IP core of FIR and DDS module
AD7612V3
- Verilog Code of AD7612
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
Each-module-program
- 此程序为基于FPGA乐曲演奏电路设计的VHDL程序，可根据程序手动控制播放的音乐-This program tracks performance FPGA-based VHDL circuit design process, according to the manual control of the music program
USB_FPGA
- 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)